Dr. DI Heinz Seyringer
"Fabrication and characterization of SiGe devices"
This thesis is devoted to the characterization and structuring of SiGe samples. In the first part surface morphology of SiGe epilayers has been studied. As described in the second part, by optimizing the lithographic techniques, it was possible to create structures with a minimal feature size below 15nm.
An emphasis in the first part of the thesis was the surface characterisation of SiGe samples. The cross-hatch-pattern, which evolves on SiGe graded buffers, causes a surface modulation of several ten nanometers. This leads to problems with depth of focus during electron beam exposure. Therefore the main effort was to reduce this surface modulation. It was shown that various growth problems are responsible for different characteristic surface morphologies which allow the identification and elimination of the problem. Furthermore, the surface roughness is much smaller with flat Ge gradients than with steep gradients.
In the next step the lithographic technology had to be improved. In electron beam lithography, the software is a very important tool since it controls the beam and hence the whole exposure. Because of several problems with the originally used software, a new program had to be developed. Extensive time-dependent current measurements gave important hints concerning the emission of LaB6-cathodes. Together with the investigation related to the proximity effect this allowed an improvement in structure size by one order of magnitude. Both in PMMA and in negative photoresist, it was possible to realize structures below 15nm.
As potential applications, three examples have been realized. First of all, these small structures can be used to create small windows in silicon dioxide films on silicon substrates. By growing germanium on these prestructured substrates, germanium dots grow only in the windows. By using electron beam lithography, these windows can be made small enough to contain only one single dot and by further decreasing the size of the windows, the size of Ge dots can be reduced.
Another application is the creation of gates for transistors. The smaller the gate length is, the smaller is the channel length between source and drain and the faster is the transistor. It should be noted that reducing gate length leads to a high gate resistance. However, this can be handled by using T-gates.
The third application was the structuring of antidots into hall bars. By measuring the resistance in dependence of the magnetic field, commensurability oscillations may be observed. These oscillations depend on the effective size of the antidots which is also determined by the defects caused by reactive ion etching. In an improved experiment this dependence might be used to optimize the etching parameters.