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ISMVL

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In May 2018, we are organizing the 48th IEEE International Symposium on Multiple-Valued Logic in Linz. Find out more at this page!

Contact

Johannes Kepler University Linz
Integrated Circuit and System Design
Univ.-Prof. Dr. Robert Wille
Altenberger Straße 69 | SCP3 0405
4040 Linz | Austria
robert.wille@jku.at
Tel: +43 732 2468 4739

Map and directions to JKU


Position Indication:

Content

Summer Semester 2016

VL+Ü Computer Architecture 1

Course IdTitleTypeWeekly HoursTeachersRhythm
336009 course registration for Computer Architecture 1
show schedule
VO3,00Robert WilleWeekly
Veranstalter: Robert Wille, Alwin Zulehner

Ziele:
In der Vorlesung werden die Grundlagen von Rechnerarchitekturen und Prozessoren vermittelt. Dies beinhaltet insbesondere:

  • Rechnersichten
  • Assembler
  • Aufbau und Funktionsweise: Hardware, Software
  • Maschinensprache
  • Kodierung von Zeichen und Zahlen
  • Prozessoraufbau
  • Komponenten des Prozessors
  • Pipelining
  • Speicherorganisation
  • Leistungsbewertung
Die Übung begleitet die Vorlesung durch praktische Aufgaben, welche die jeweiligen Konzepte illustriert.
Übungsblätter

Ort und Zeit:
  • Vorlesung:
    • Do, 10:15-12:30 HS 18
  • Übung:
    • Do, 12:45-13:30 S3 055
    • Do, 13:45-14:30 S3 055
    • Do, 14:30-15:15 S3 055
    • Do, 15:30-16:15 HS 8
Weitere Informationen:
  • Kontakt: robert.wille@jku.at
  • ECTS: 4,5 V+1,5 Ü
  • Stunden: 3 V+1 Ü
  • Sprache: Deutsch
  • Studiengänge: Bachelor 2. Jahr Informatik

VL+Ü Hardware Design

Course IdTitleTypeWeekly HoursTeachersRhythm
336012 course registration for Digital Hardware Design
show schedule
VO2,00Robert WilleWeekly
336013 course registration for Digital Hardware Design
show schedule
UE1,00Andreas RaucheneckerWeekly
Lecturers: Robert Wille, Andreas Rauchenecker

Goals:
Obtaining an overview of the main steps in the design of circuits and systems as well as receiving basic knowledge in digital chip design using the hardware description language VHDL.

Content:

  • Lecture:
    • Design of Systems
    • Target Architectures for HW/SW Systems
    • Allocation, Binding, Scheduling
    • Partitioning
    • Overview: Software Design (Code Generation, Register Allocation)
    • Hardware Design
    • Abstraction Levels
    • Hardware Description Languages (VHDL, SystemC)
    • Synthesis
    • Verification
    • Debugging
    • Test
  • Exercise
    • -VHDL
    • - Design flow for FPGA applications
    • - Limitations in digital hardware
    • - Exercises for practical utilization of the newly learned skills
Place and Time:
  • Lecture:
    • Thu, 08:30-10:00 MT 132
  • Excercise:
    • Fri, 09:15-10:00 HS 15
Further Information (in German):
Im diesem Sommersemester wird die LVA „Digitaler Hardwareentwurf“ (Pflicht im Bachelor-Studium, 6. Semester) mit der bisherigen Informatik-LVA „Hardware Design“ neu konzipiert und aufgestellt. Dies führt dazu, dass beide LVAs in KUSSS noch getrennt gelistet (gespiegelt) werden, es sich de facto aber um die gleiche Veranstaltung handelt (identische Dozenten, Vorlesungs- und Übungstermine). Außerdem wird die LVA nun in englischer Sprache angeboten.

  • Contact: robert.wille@jku.at
  • ECTS: 3,0 V+1,0 Ü
  • Amount: 2 V+1 Ü
  • Language: Englisch
  • Studies:
    • Informationselektronik (Bachelor)
    • Informatik (Master)
    • Mechatronik (Bachelor)

Seminar in Computational Engineering

Course IdTitleTypeWeekly HoursTeachersRhythm
336052 course registration for Seminar in Computational Engineering Design of Digital Circuits and Systems
show schedule
SE2,00Robert Wille
Alexandru Paler
Weekly
Lecturer: Robert Wille

Goals:
In the seminar, we will take an in-depth look into the design of circuits and systems and their underlying tasks/problems. To this end, selected topics will be addressed which also provide an insight into currently considered research tasks. This includes (but is not limited to) the following design tasks and problems (further topics are explicitly welcomed):

Content:

  • Descriptions for Circuits and Systems (e.g. HDLs)
  • Assembler Programming
  • Test & Verification
  • Algorithms & Data-structures for Design Tasks
  • Boolean Algebra and its Applications
  • Reasoning Engines and Decision Procedures
  • Solutions for Optimization and Search Problems
  • Alternative Computing Paradigms (e.g. Quantum Computing, DNA Computing, etc.).

Next Seminar: Thursday, June 16, 2016, 15:00, room 409 (Science Park 3, 4th floor)

Further Informationen: