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ISMVL

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In May 2018, we are organizing the 48th IEEE International Symposium on Multiple-Valued Logic in Linz. Find out more at this page!

Contact

Johannes Kepler University Linz
Integrated Circuit and System Design
Univ.-Prof. Dr. Robert Wille
Altenberger Straße 69 | SCP3 0405
4040 Linz | Austria
robert.wille@jku.at
Tel: +43 732 2468 4739

Map and directions to JKU


Position Indication:

Content

Summer Semester 2017

VL+Ü Computer Architecture 1

Course IdTitleTypeWeekly HoursTeachersRhythm
336009 course registration for Computer Architecture
show schedule
VO3,00Robert WilleWeekly
336010 course registration for Computer Architecture
show schedule
UE1,00Alwin Walter ZulehnerWeekly
336021 course registration for Computer Architecture
show schedule
UE1,00Alwin Walter ZulehnerWeekly
336025 course registration for Computer Architecture
show schedule
UE1,00Andreas GrimmerWeekly
336027 course registration for Computer Architecture
show schedule
UE1,00Andreas GrimmerWeekly
Veranstalter: Robert Wille, Alwin Zulehner

Ziele:
In der Vorlesung werden die Grundlagen von Rechnerarchitekturen und Prozessoren vermittelt. Dies beinhaltet insbesondere:

  • Rechnersichten
  • Assembler
  • Aufbau und Funktionsweise: Hardware, Software
  • Maschinensprache
  • Kodierung von Zeichen und Zahlen
  • Prozessoraufbau
  • Komponenten des Prozessors
  • Pipelining
  • Speicherorganisation
  • Leistungsbewertung
Die Übung begleitet die Vorlesung durch praktische Aufgaben, welche die jeweiligen Konzepte illustriert.

Ort und Zeit:
  • Vorlesung:
    • Do, 10:15-12:45 HS 18
  • Übung:
    • Do, 12:45-13:30 S3 055
    • Do, 13:45-14:30 S3 055
    • Do, 14:30-15:15 S3 055
    • Do, 15:30-16:15 S3 055
Weitere Informationen:
  • Kontakt: robert.wille@jku.at
  • ECTS: 4,5 V+1,5 Ü
  • Stunden: 3 V+1 Ü
  • Sprache: Deutsch
  • Studiengänge: Bachelor 2. Jahr Informatik

VL+Ü Hardware Design

Course IdTitleTypeWeekly HoursTeachersRhythm
336004 course registration for Hardware Design
show schedule
VL2,00Robert WilleWeekly
336031 course registration for Hardware Design
show schedule
UE1,00Andreas RaucheneckerWeekly
Lecturers: Robert Wille, Andreas Rauchenecker

Goals:
Obtaining an overview of the main steps in the design of circuits and systems as well as receiving basic knowledge in digital chip design using the hardware description language VHDL.

Content:

  • Lecture:
    • Design of Systems
    • Target Architectures for HW/SW Systems
    • Allocation, Binding, Scheduling
    • Partitioning
    • Overview: Software Design (Code Generation, Register Allocation)
    • Hardware Design
    • Abstraction Levels
    • Hardware Description Languages (VHDL, SystemC)
    • Synthesis
    • Verification
    • Debugging
    • Test
  • Exercise
    • VHDL
    • Design flow for FPGA applications
    • Limitations in digital hardware
    • Exercises for practical utilization of the newly learned skills
Place and Time:
  • Lecture:
    • Thu, 08:30-10:00 MT 132
  • Excercise:
    • Fri, 09:15-10:00 HS 18
  • Contact: robert.wille@jku.at
  • ECTS: 3,0 V+1,0 Ü
  • Amount: 2 V+1 Ü
  • Language: Englisch
  • Studies:
    • Informationselektronik (Bachelor)
    • Informatik (Master)
    • Mechatronik (Bachelor)

Seminar in Computational Engineering

Course IdTitleTypeWeekly HoursTeachersRhythm
336052 course registration for Seminar in Computational Engineering Design of Digital Circuits and Systems
show schedule
SE2,00Robert WilleBlock

Goals:
The design of circuits and systems offers a wide field of interesting tasks -- ranging from questions how to describe the desired circuits and systems, over their implementation and realization, up to their test and verification. Since the resulting electronic systems can basically be found "everywhere" in our daily live, these tasks have an important industrial and academic relevance. In this seminar, we will take an in-depth look into selected areas of the design of circuits and systems and their underlying tasks/problems. Students with various backgrounds (theoretical, conceptual, algorithmical, implementational, technical, etc.) will certainly be able to make contributions to this seminar. Moreover, this seminar is a good opportunity to get familiar with topics for following projects and/or Bachelor/Master theses.

Content:
Possible topics include (but are not limited to):

  • Descriptions for Circuits and Systems (e.g. HDLs)
  • Assembler Programming
  • Algorithms & Data-structures
  • Boolean Algebra and its Applications
  • Reasoning Engines and Decision Procedures
  • Test & Verification
  • Solutions for Optimization and Search Problems
  • Alternative Computing Paradigms (e.g. Quantum Computing, DNA Computing, etc.).
The seminar will be conducted as a block. To this end, we will first have an initial meeting at the beginning of March in which we will discuss the details (including timing, etc.). In order to participate, we kindly ask for a registration in KUSSS. Afterwards, we will contact all interested students with a proposal for a date/time of the initial meeting. For any questions, feel free to contact robert.wille(/\t)jku.at.

Next Seminars: End of July: Deadline for the written summary

Further Informationen: