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Christian Doppler Laboratory for Digitally Assisted RF Transceivers for Future Mobile Communications.

for Digitally Assisted RF Transceivers for Future Mobile Communications.

In January 2017, the Institute of Signal Processing and the Institute for Communications Engineering and RF-Systems established the Christian Doppler (CD) Laboratory for Digitally Assisted RF Transceivers for Future Mobile Communications. The lab has a total duration of seven years and an overall budget of € 4.700.000.-. The CD laboratory is dedicated to basic and applied research on digital signal processing (DSP) methods for radio frequency (RF) transceivers. With current Complementary Metal-Oxide-Semiconductor (CMOS) technology, DSP methods are perfectly suited to compensate analog imperfections appearing in RF circuits, to introduce advanced signal processing methods not feasible with analog circuits, and to benefit from technology scaling in terms of computing performance, power consumption and chip area. RF transceivers in current commercial products already make use of DSP. The continuously increasing requirements for mobile devices, e.g. from the 4th generation (4G) mobile communications standard “Long Term Evolution” (LTE) and the currently implemented 5G standard, will strongly increase this need in future developments. A common result of these requirements is both a significant rise in complexity of the transceiver architectures and a substantially increasing number of possibilities for self-interference. In the CD laboratory we tackle these issues by making use of DSP and focus our research in three areas:

Christian Doppler Laborator

for Digitally Assisted RF Transceivers for Future Mobile Communications.

Heads of Laboratory

Univ.-Prof. DI Dr. Mario Huemer
Science Park 3, 0523
Phone: +43 732 2468 5681


Univ.-Prof. DI Dr. Andreas Springer, opens an external URL in a new window
Science Park 1, 0351
Phone: +43 732 2468 6371




Jan. 2017 - Dec. 2023

Area 1: Receiver (RX) Interference Cancellation: We develop methods to identify and cancel interference in the receivers by digital or mixed signal concepts.

Area 2: Energy Efficient Digitally Assisted Transmitter (TX) Architectures: Digitally assisted transmitter architectures need to be explored to accommodate channel bandwidths well beyond 20 MHz for high data rate applications.

Area 3: All-Digital Phase-Locked Loops: Improved all-digital phase-locked loops (ADPLLs) are required, e.g. to reduce the number of digitally controlled oscillators in a transceiver chip. Furthermore, the reduction of the power consumption of ADPLLs is targeted to enable low-cost RF transceivers for Internet of Things devices.

While each of these three strands of research has its own specifics, complexity and interference issues are linking them together and make them to some extent depend on each other. Furthermore, system-level time- and frequency domain modeling and statistical signal processing methods are common research methods applied across the different topics. Outcomes of our CD-laboratory are DSP algorithms, architectures, methods, and in selected cases prototype implementations for RX, TX and ADPLL which allow the realization of RF transceivers fulfilling the increasing requirements on user experience like data rate and seamless connectivity while reducing chip area, power consumption and design complexity.

The block diagram depicts a typical RF transceiver and visualizes the three research areas addressed above. Area 1 is handled by the ISP, area 2 is executed in co-operation of both institutes, and area 3 is conducted by Prof. Springer’s institute. In the following the three areas are described briefly.

  • Receiver Interference Cancellation

One of the main reasons for receiver desensitization in frequency-division duplex (FDD) transceivers is the limited isolation between the transmitter(s) and the receiver(s). The resulting transmitter leakage into the receiver paths can be identified as the root cause of several receiver interferences. With the introduction of carrier aggregation to support higher data rates the number of severe transmitter induced interference problems has even reached a new dimension, and the challenges will further exacerbate in 5G and beyond RF transceivers.

In this area mathematical models of the different types of interferences are developed, and fully digital as well as mixed signal based interference cancellation methods are investigated. We develop adaptive and flexible architectures and aim to relax the requirements on the analog components. Also complexity considerations play a crucial role, since the algorithms have to run in real-time on battery powered mobile communication devices. Especially for nonlinear problems it is not always straightforward to derive a perfectly accurate mathematical model, therefore we currently, in parallel to model based approaches, also investigate data based machine learning concepts for self-interference cancellation.

The main focus of our investigations in this area is on the cancellation of TX induced self-interference, but concepts to mitigate other types of interferences (such as, e.g., WiFi blockers) are also investigated.

  • Transmitter Architectures

Area 2 has its focus on signal processing concepts for digitally assisted transmit architectures. The aim of this area is to investigate and optimize novel architectures based on radio frequency digital-to-analog converters (RF-DACs) which are used to replace traditional mixers in the transmit path. Basically, we can distinguish between two topologies, the IQ-RF-DAC and the polar-RF-DAC, each with its own advantages and disadvantages. We furthermore explore new architectures, which try to combine the advantages of both concepts. The goal is to enable the efficient use of RF-DACs for LTE and 5G waveforms. Since these standards have stringent requirements on spectral purity, we particularly investigate digital pre-distortion methods to linearize the transmitters.

  • Frequency Synthesis

Area 3 focuses on the advancement of ADPLLs as a major building block in RF transceivers. Research is conducted to improve spectral purity, frequency coverage, and settling time of ADPLLs. For polar transmitter architectures the target is to improve the modulation bandwidth of the ADPLL to cover the increasing bandwidths appearing in LTE carrier aggregation modes and in 5G. For low-power Internet of Things (IoT) applications the power consumption of ADPLLs needs to be reduced significantly.