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Spurs Mitigation in Digital-to-Time Converters

Spurs Mitigation in Digital-to-Time Converters

Project description

A major building block in transceivers (TRX) for mobile devices is the phase-locked loop (PLL). In the receiver (RX) path, the PLL can be used for generating a very high and stable frequency (frequency synthesis). In the transmitter (TX), especially in a polar transmitter in which the modulated transmit signal is generated by applying phase and amplitude modulation, the PLL can be used to generate the phase-modulated signal. With evolving mobile communication standards and the need of supporting as many as possible radio access technologies, TRX’s in current mobile devices have several PLL’s, because it is not possible to cover the required wide frequency range with one single PLL. Many PLL’s on one chip lead to problems like large chip area consumption or crosstalk issues. One possible solution might be the combination of a PLL with a Digital-to-Time Converter (DTC). In a DTC-based TRX architecture only one PLL is needed which is driving multiple DTC’s in the RX and TX paths. However, the DTC has its own challenges and one of them is the appearance of spurious tones (spurs). The major aim of this project is to investigate all kinds of spurs cancellation techniques in a DTC-based TRX architecture.

Spurs Mitigation in Digital-to-Time Converters


Dec. 2014 - Dec. 2016