Das Institut für Complex Systems beschäftigt sich mit verlässlicher Elektronik. Der Forschungsschwerpunkt liegt hierbei insbesondere darin, die Korrektheit von Hardware im Zusammenspiel mit Software abzusichern.
Aktuell befindet sich das Institut noch in der Aufbauphase.
Institut für Complex Systems
Johannes Kepler Universität Linz
Altenberger Straße 69
Aubrunnerweg 3B, 1. Stock
+43 732 2468 4561
- Nov 18, 2020: There are still several open PhD positions at the institute. If you are interested please contact Prof. Daniel Große.
- Nov 17, 2020: Our work on “Clustering-guided SMT(LRA) learning” is presented at the International Conference on integrated Formal Methods (iFM)
- Nov 9, 2020: Our work on “ASNet: Introducing approximate hardware to high-level synthesis of neural networks” is presented at the International Symposium on Multiple-Valued Logic (ISMVL)
- Oct 27, 2020: Daniel Große speaks in the tutorial "Cross-Level Compliance Testing and Verification for RISC-V" at the Design and Verification Conference and Exhibition Europe (DVCon)
- Oct 21, 2020: Our work on „RVX - A Tool for Concolic Testing of Embedded Binaries Targeting RISC-V Platforms“ is presented at the International Symposium on Automated Technology for Verification and Analysis (ATVA)
- Oct 20, 2020: Daniel Große has been appointed as Program Committee Member of the Design Automation Conference (DAC) 2021
- Oct 20, 2020: Our work on “Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime” is presented at the International Conference on Computer Design (ICCD)
- Sep 17, 2020: We received the Best Paper Award for our paper "Efficient cross-level testing for processor verification: A RISC-V case-study" at the Forum on specification & Design Languages (FDL) 2020
- Sep 17, 2020: Daniel Große has been appointed as Program Chair of the Forum on specification & Design Languages (FDL) 2021
- Sep 9-10, 2020: Our work on “Early Verification of ISA Extension Specifications using Deep Reinforcement Learning” and “Verification of Embedded Binaries using Coverage-guided Fuzzing with SystemC-based Virtual Prototypes” are presented at the ACM Great Lakes Symposium on VLSI (GLSVLSI)
- Jul 20-24, 2020: Our work on “Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side”, “Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes” and “Verification for Field-coupled Nanocomputing Circuits” are presented at the Design Automation Conference (DAC)