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Lehre - Wintersemester 2020

Seminar in Computational Engineering:
Design and Verification of RISC-V Processors and Platforms

Objectives:
Stimulated from the enormous momentum of open-source software, a counterpart on the hardware side recently emerged: RISC-V is an open and royalty-free Instruction Set Architecture (ISA) and as such defines the interface between the hardware and software. Since 2015, the RISC-V ISA standard is maintained by the non-profit RISC-V foundation, which has more than 580 members -- among them are also many software companies like Google -- aiming for innovation. RISC-V features an extremely modular and extensible design that provides enormous flexibility in building application-specific solutions targeting all kinds of systems: microcontrollers, accelerators for deep learning, or safety-critical systems. This spectrum demands for novel design and verification approaches spanning from software engineering down to the hardware design.

Topics:
In this seminar, we will consider recent research in the design and verification of RISC-V processors and platforms. Possible topics include (but are not limited too):

  • Design of RISC-V processors using new hardware design languages like e.g. SpinalHDL

  • Instruction stream generation for RISC-V cores

  • Compliance Testing

  • Formal verification of RISC-V cores

  • Hardware/software co-verification using e.g. SystemC-based Virtual Prototypes

The Institute for Complex Systems is very active in the field of RISC-V (see our website http://www.systemc-verification.org/risc-v for a compact summary of our RISC-V related approaches).

The seminar will be conducted as a block. We will have an initial meeting in October where we will discuss the details (also the seminar schedule). For participation in the seminar please register in KUSSS. We will then contact all interested students with a proposal for the initial meeting.

Next Seminar: tba

Further Information:

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