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Univ.-Prof. Dr. Daniel Große

Research Interests

  • Electronic Design Automation (EDA)
  • Instruction set architecture RISC-V
  • Modelling (UML, SystemC, (System)Verilog, VHDL)
  • Virtual Prototpying and Transaction Level Modeling (TLM)
  • Simulation-based verification (UVM, Constrained Random Simulation)
  • Formal verification (Model Checking, Equivalence Checking)
  • Symbolic Computer Algebra (SCA)
  • (Functional) coverage
  • Automated debugging
  • Approximate Computing
  • Algorithms and data structures (SMT, SAT, BDD)
  • Emerging technologies